Maxim DS5001FP Guide de l'utilisateur télécharger pdf (Page 10)

DS5001FP

10 of 27

Figure 5 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this

configuration, both program and data are stored in a common RAM chip Figure 6 shows a similar system

with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The

bidirectional byte-wide data bus connects the data I/O lines of the SRAM.

Figure 5. CONNECTION TO 128k x 8 SRAM

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 26 27

Pas de commentaire

Maxim DS5001FP Guide de l'utilisateur Page 10