Maxim MAX5865 Manuel d'utilisateur télécharger pdf (Page 18)

MAX5865

Mode Recovery Timing

Figure 6 shows the mode recovery timing diagram.

WAKE

is the wake-up time when exiting shutdown, idle,

or standby mode and entering into Rx, Tx, or Xcvr

mode. t

ENABLE

is the recovery time when switching

between any Rx, Tx, or Xcvr mode. t

WAKE

or t

ENABLE

the time for the ADC to settle within 1dB of specified

SINAD performance and DAC settling to 10 LSB error.

WAKE

or t

ENABLE

times are measured after the 8-bit

serial command is latched into the MAX5865 by CS

transition high. t

ENABLE

for Xcvr mode is dominated by

the DAC wake-up time. The recovery time is 10µs to

switch between Xcvr, Tx, or Rx modes. The recovery

time is 40µs to switch from shutdown or standby mode

to Xcvr mode.

System Clock Input (CLK)

CLK input is shared by both the ADCs and DACs. It

accepts a CMOS-compatible signal level set by OV

from 1.8V to V

. Since the interstage conversion of the

device depends on the repeatability of the rising and

falling edges of the external clock, use a clock with low

jitter and fast rise and fall times (<2ns). Specifically,

sampling occurs on the rising edge of the clock signal,

requiring this edge to provide the lowest possible jitter.

Any significant clock jitter limits the SNR performance

of the on-chip ADCs as follows:

where f

represents the analog input frequency and

is the time of the clock jitter.

SNR

IN AJ

=×

×× ×













log

Ultra-Low-Power, High-Dynamic-

Performance, 40Msps Analog Front End

18 ______________________________________________________________________________________

Figure 5. 3-Wire Serial Interface Timing Diagram

MSB

SCLK

DIN

LSB

CSW

CSS

Figure 6. MAX5865 Mode Recovery Timing Diagram

SCLK

DIN

ID/QD

DAO–DA7

8-BIT DATA

ADC DIGITAL OUTPUT.

SINAD SETTLES WITHIN 1dB

DAC ANALOG OUTPUT. OUTPUT

SETTLES TO 10 LSB ERROR

WAKE, SD, ST_ (Rx)

OR t

ENABLE, Rx

WAKE, SD, ST_ (Tx)

OR t

ENABLE

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Maxim MAX5865 Manuel d'utilisateur Page 18

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