Maxim DS33Z41 Manuel d'utilisateur

1 of 44 REV: 110106 GENERAL DESCRIPTION The DS33Z41 design kit is an easy-to-use evaluation board for the DS33Z41 Ethernet transport-over

DS33Z41DK 10 of 44 BASIC OPERATION Powering Up the Design Kit • Attach DS21458 resource card to main board. • Connect PCB 3.3V and GND banana plug

DS33Z41DK 11 of 44 Quick Setup #1 (Device Driver + DS21458 T1/E1) • Select TCLK source for the DS21458 resource card. If this is the only DS33Z41

DS33Z41DK 12 of 44 CONFIGURATION SWITCHES AND JUMPERS The DS33Z41DK has several configuration switches, banana plugs, oscillators, and jumpers. Tabl

DS33Z41DK 13 of 44 BASIC SETTING SILKSCREEN REFERENCE FUNCTION SW MODE HW MODE DESCRIPTION spi_cs, spi_ck, spi_miso, spi_mosi — — — SPI signals (f

DS33Z41DK 14 of 44 ADDRESS MAP (ALL CARDS) Motorola resource card address space begins at 0x81000000. All offsets given below are relative to the be

DS33Z41DK 15 of 44 CONTROL REGISTERS Register Name: delay_line1, delay_line2, delay_line3, delay_line4 Register Description: DS33Z41 frame delay R

DS33Z41DK 16 of 44 DS33Z41 INFORMATION For more information about the DS33Z41, consult the DS33Z41 data sheet available on our website at www.maxim-

DS33Z41DK 17 of 44 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxi

PAGES 5-10P2 CONNECTOR (PLUG)MOTHERBOARD CONNECTORS FOR WAN R.C.P1 CONNECTOR (PLUG)HIERARCHICAL BLOCKDS33Z11/Z41 TOP LEVELZ44_RSER<1>Z44_TCLK<

PAGES 13-19GNDV3_3I47A_DUT<11..0>D_DUT<7..0>CS_X1BTS_DUTBIS1_DUTBIS0_DUTWR_DUTRD_DUTINT5INT4INT3INT2TMS_NUTDI_NUTDO_NUTCK_NUXD<7..0>

DS33Z41DK 2 of 44 TABLE OF CONTENTS GENERAL DESCRIPTION...

(INPUT)PROC (FPGA) AUTOMATICALY IMPLEMENTS BUS MODEHW MODE PINS ARE OUTPUTS FROM Z MODULE TO PROCLED+TP(OUTPUT)DS33Z11/Z413C2^3D2^5B1<3C2^3D2^5B2&l

SD_CLKO MAY BE DELAYEDAND CONNECTINGBY REMOVING 0 OHM RESISTORJUMPERS WITH 75 OHM COAXUNMARKED RESISTORS ARE 30 OHMS30SD_CLKII228NADS33Z1110UFV1_8ZCHI

MT48LC4M32B2 - 1 MEG X 32 X 4 BANKSSYNCHRONOUS DRAMFROM Z11 SYSCLKO09101101313021345768910111221314151617181920213222324252627282945678SD_DQ<31..0&

CHASSIS GND FOR PHYHIERARCHICAL BLOCKPAGES 11-12I70I69100O100MZH100O100MZH10UF10UF0.1UFTX_CLK<1>TX_EN<1>LED_DPLX_A0<1>RXD2<1>R

CONNECT ANYWHERESIGNAME_TRI DOES NOTMOTOROLA NON-MUX, MII, FULL DUPLEX, 100 MBIT, AUTO-FLOW CONTROLMODE (SHOWN BELOW SIGNAL) RESULTS IN:LOWLOWHIGHHIGH

0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UF0.1UFI391UF1UF1UF1UF10UF1UF1UFBLACK BLACKI38RED0.1UF0.1UF0.1UF0.1UFREDV1_8ZCHIP1UFV1_

0.2 BETWEEN CONNECTORS.ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOWON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING A

SHOULD BE PLACED CLOSE TO PHYRESISTORS FOR TD+-/RD+-SHOULD BE PLACED CLOSE TO XFRMCAPS FOR XFRM CENTER TAPDNPRX_ERRRD_PBUFFERBUFFER.1UF30TD_PSYM_1.1UF

PROCESSOR RESOURCE CARDMMC2107I6412121415221PD<31..0>2PA<22..0>VDDSYNGND141516I6811121316181719182021101798762324252628192729303154320200.

FLASH ENABLEINTERNALXTAL W/ PLLMASTER MODEFULL DRIVERESET CONFIGURATIONBOOTINTERN/EXTERNBOOT EXTBOOT INTERNALWHEN SET FORD18 HAS A 10.5K LOAD TO V3VRE

DS33Z41DK 3 of 44 COMPONENT LIST Table 1 shows the component list for the DS33Z44 and DS33Z11/DS33Z41 design kits and resource cards. This BOM conta

JTAG CONFIGURATIONALIGN KEYPINONCETDIMMC2107ONCETDOPINTDI...FPGA+FLASH...BUT DO NOT POPULATEPLACE PADS FOR CAP10UF5.61UF1UF1UF1UF.1UF8.0MHZI471.0M1UF1

REDREDRED121212876313029282726251624232221205432115016171819RED14REDRED330330330330GREEN5134321543211211109OERWTACS1CS2EB0EB1CS0TEASCI2_INSCI2_OUTSPAR

RW ALSO FUNCTIONS AS ALT_RD_DSWE ALSO FUNCTIONS AS ALT_WR_RWBUS MODEDETECTION (DUT AT CS_X2)D_DUT<7..0>A_DUT<11..0>50CS_X2BTS_DUTWR_DUTALE

MBVERCS_X1CS_X6RD_DUTWR_DUTCS_X2CS_X3ALE_DUTCS_X5CS_X4SSSCKMISOMOSIRESET_BD_DUT<7..0>0123765421010K10K10K10K7654A_DUT<11..0>111098A_DUT<

DONECCLKXRSTJTD_SPART2FLASHXI_TMSV2_5XI10UF3301UF1UF1UF.1UF.1UF.1UF1UF.1UF.1UF.1UF.1UF1UF1UF1UF1UF1UFTMS_NUTDO_NUTDI_NU10KJTD_FLASH_TDOX_INITCFG_DINCC

DS21458 WAN INTERFACE BLOCK2.048MHZ_3.3VRB160RB184LIUCMCLKMCLK3030ONCE_TCLKI73RESET_AH10UF10UF0.1UF0.1UF0.1UFWRCS0.1UF0.1UFRESET_B0.1UF0.1UFESIBR0ESIB

PORT1_RRING = PIN L1PORT2_RRING = PIN F16RLOS1TRING2TTIP2TRING1TTIP1RRING1TCLK1RTIP1TSER1RCLK1RSER1RRING2RSER2RLOS2RSYNC2TCLK2RTIP2TSER2TSYSCLK2RSYSCL

PORT4_RRING = PIN T11PORT3_RRING = PIN A6TSYSCLK3TSYSCLK4TSSYNC4RSYSCLK4TTIP3RCLK4TRING4TTIP4TRING3RRING4RSER4RLOS4RSYNC4TCLK4RTIP4TSER4RRING3RLOS3RSY

THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28-30 AND 23-25AS THE TX PRIMARY. THIS HAS BEEN CORRECTED IN THE SCHEMATIC,THE PCB / ASSEMBLY HAS B

THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28-30 AND 23-25THE PCB / ASSEMBLY HAS BEEN MODIFIED TO ACCOMMODATE THIS.AS THE TX PRIMARY. THIS HAS

DS33Z41DK 4 of 44 DESIGNATION QTY DESCRIPTION SUPPLIER PART H9–H16 16 KIT, 4-40 HARDWARE, 1.12 NYLON STANDOFF AND NYLON HEX-NUT (1.12 STANDOFF PN

ALL UNMARKED BIAS RESISTORS ARE 10KMOTNOTMUXRLOS1RLOS2RLOS3RLOS4LIUCESIBRDESIBR0ESIBR1MUXBTS2.0K2.0K2.0K3302.0K3303303302.0K2.0KRB185RB209RB192RB228DS

XRSTDONECCLKJTD_SPART2FLASHONCE_TCLKJTD_SPART_TDIXI_TMS0.1UF0.1UF0.1UF0.1UF.1UF.1UF0.1UF0.1UFJTDO458JTD_SPART_TDIONCE_TCLKXI_TMSTDI_NUX_INITCFG_DIN.1U

TSER PULLDNS USED IN IBO MODE(IMPLEMENTS IMUX)TSER1CFG_DINRGAPCLK4RGAPCLK3RGAPCLK2RGAPCLK1TSSYNC4TSSYNC1BPCLK1RSYSCLK1RSYSCLK2TSYSCLK3RSYSCLK3RSYSCLK2

PORTS ARE ENABLED BY DEFAULT ON T1 BRD, AND ARE DISABLED USING JUMPERS ON T3 BRDWRZ41TSYNC530OBS_TCLK<3>OBS_RSER<3>OBS_RDEN<4>30Z44_

P1 CONNECTOR (RECEPTICAL)P2 CONNECTOR (RECEPTICAL)WAN R.C. CONNECTOR TO MOTHERBOARDNOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4RECEPTACLEGNDINT2RESET

DS33Z41DK 5 of 44 DESIGNATION QTY DESCRIPTION SUPPLIER PART R13–R15, R18–R20, R22, R23, R29, R30, RB01, RB03, RB07, RB09, RB15–RB17, RB30–RB32, R

DS33Z41DK 6 of 44 DESIGNATION QTY DESCRIPTION SUPPLIER PART R85, R88, R94, R104, R113, RB02, RB04–RB06, RB08, RB39, RB45, RB46, RB56, RB63–RB70,

DS33Z41DK 7 of 44 DESIGNATION QTY DESCRIPTION SUPPLIER PART UX01–UX12, UXB02–UXB04, UXB06–UXB08 18 HIGH SPEED BUFFER Fairchild NC7SZ86 UXB01,

DS33Z41DK 8 of 44 Figure 1. System Floorplan Figure 2 shows the DS21458 quad T1/E1 PC board floorplan. The current confi

DS33Z41DK 9 of 44 PC BOARD ERRATA • Silkscreen for JTAG connector signal descriptions is incorrect on the quad T1/E1 card. This should be corrected