Maxim /MAX4889A Spécifications Page 11
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
PCIe/104 and PCI/104-Express Specification Revision 3.0 February 17, 2015 Page 10
Glossary of Terms
Terms Definitions
ATX Advanced Technology Extended
A specification for PC motherboards, power supplies, and system chassis. One of its most
notable features is support for “Standby” and “Soft-Off” power savings modes.
Device A logical device attached to a PCI Express Link. Generally an add-in card.
DMA Direct Memory Access
A method for peripherals to efficiently access system memory without CPU intervention.
EBX Form factor for SBC’s
Host The central connection of a PCI Express system, typically a CPU module. This is called the
“Root Complex” by the PCI Express specification.
ISA Bus Industry Standard Architecture
A legacy bus used on earlier PCs. It has been phased out of desktop PCs, but is still common in
embedded systems.
Lane Fundamental unit of a PCI Express connection. A set of differential signal pairs, one pair for
transmission, and one pair for reception. Multiple lanes may be combined to increase
bandwidth (up to x16). A “by-N Link” is comprised of N Lanes.
Link The collection of one or more PCI Express Lanes, plus an additional differential pair for a
clock, which make up a standard PCI Express interconnect. According to PCI Express
Specification 1.1 a Link can be comprised of 1, 4, 8, or 16 Lanes.
Packet Switch A device used to attach multiple PCI Express devices to a single link on the HOST. The PCI
Express Specification refers to this simply as a “Switch.” In this document, the term “Packet
Switch” is used to differentiate from a “Signal Switch.”
PCIe PCI Express
PEG PCI Express Graphics
SBC Single Board Computer
SDVO Serial Digital Video Output used from Intel 915/945/965 chipsets
Signal Switch An analog switch used to select between multiple PCI Express devices to attach to a single PCI
Express link, or multiple links to attach to a single device. Also called a “Channel Switch.”
SMBus System Management Bus
USB Universal Serial Bus
LPC Low pin count bus, a bus specification for legacy devices
SATA Serial ATA Bus
- Version 3.0 1
- TRADEMARKS AND COPYRIGHTS 2
- REVISION HISTORY 3
- TABLE OF CONTENTS 5
- TABLE OF FIGURES 8
- TABLE OF TABLES 10
- Glossary of Terms 11
- 1. INTRODUCTION 12
- Purpose 12
- Standard Identification 12
- Description 12
- PCIe/104 Type 1 and Type 2 13
- PCI/104-Express Feature Set 14
- General Stacking Rules 14
- PCIe/104 Feature Set 14
- PCIe/104 15
- 1.9.2 SATA Links 16
- 1.9.3 LPC Bus 16
- 1.9.5 System Management Bus 17
- References 18
- 2. EXPANSION CONNECTOR A 19
- Functions 19
- Signal Descriptions 20
- Signal Naming Convention 21
- Pin Assignment 22
- 2.4.1.1 Two x8 or x4 Links 25
- 2.4.2 PEG_ENA# Signal 26
- 2.4.3 DIR Signal 26
- 2.4.3.1 DIR Line on Host 27
- 2.4.3.2 DIR Line on Device 27
- Switching 32
- System Clocking 32
- Layout Recommendations 33
- Routing Topology 34
- 2.8.2 SATA 35
- 3. EXPANSION CONNECTOR B 39
- +5V_SB, PSON#, and PME# 41
- System Stacking Rules 43
- Host Configuration Rules 43
- Stack Configuration Examples 45
- 5. ELECTRICAL SPECIFICATION 51
- Power and Ground 51
- AC/DC Signal Specifications 52
- Connector A 53
- Bottom Connector 54
- Top Connector 54
- Connector B 61
- Connector A: ASP-129637-03 66
- Top View of Module 66
- Standoff 67
- PC/104-Plus Brid 69
- PCI Device 69
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